As computer and other digital systems become more complex and more capable, methods and hardware to enhance the transfer of data between system components or elements continually evolve. Data to be transferred includes digital signals representing data, commands, addresses, or any other information. System components or elements can include different functional hardware blocks on a single integrated circuit (IC), or on different ICs. The different ICs may or may not be on the same printed circuit board (PCB). System components typically include an input/output (I/O) interface specifically designed to receive data from other system components and to transmit data to other system components.
One consistent trend as computing systems become more capable is an increase in the amount of data to be transferred per time period. Some applications that require high data rates include game consoles, high definition television (HDTV), personal computers (PCs) main memory, graphics processors, and various consumer devices not already mentioned. In response to the demand for increased data rates, double data rate (DDR) standards have been developed to standardize the behavior of hardware and software using high data rates. Several generations of graphics DDR (GDDR) standards have been developed specifically for graphics processing and video processing, which typically demand the capability to transfer and process very large amounts of data.
In some instances, it is necessary to write only a portion of the bits in a transmission. For example, in a system that transmits 32 bytes, or 256 bits per command, some but not all of the 32 bytes might be written in a write operation. This will be referred to as a byte-write operation herein. One conventional byte-write method is to read the 256 bits that are in the DRAM, modify the portion to be changed, and write all of the 256 bits back. This method is commonly used in central processing units (CPUs), and is referred to as a read-modify-write operation. Unfortunately, for high-speed applications, such as graphics applications, read-modify-write operations are both too slow and too complex to implement. One reason is that graphics processors often use a complex operation reordering schemes in order to optimize the memory interface.
So historically DRAMs provide one additional data mask pin for every eight data pins, which indicates whether the eight bit data should be written or not. This data mask method is referred to in existing DRAM specifications. One disadvantage of this method is it results in one extra pin for every eight data bit pins, thus increasing the pin count.
In addition, the existing data mask method in existing DRAM specifications is not applicable in high speed interfaces which are susceptible to data bit errors. One reason is that the errors on the data mask pins are fatal. This is due to the fact that an error on the data mask pin may result in a byte write that was not intended. The data in that byte would be destroyed (overwritten) and could not be retried. In addition, an error on the data mask will make the error detection/correction feature provided by certain DRAMs useless.
FIG. 1A is a block diagram of components of a prior art digital system 100. The components include a processor 102 and a memory component 104. The processor 102 controls the memory component 104 by communicating over an interface that includes command lines, address lines, data lines, and separate, dedicated data mask lines. The memory component 100 is a DDR memory that communicates with the processor 102 over a DDR interface.
FIG. 1B is a timing diagram illustrating a write operation 106 with a data mask, as performed by the prior art components of FIG. 1A. In this illustration, a burst-of-8 write transaction has been issued. The top waveform is the clock (CLK) waveform. The waveform below the CLK waveform shows the command waveform (CMD) on the command lines. Three write commands are shown, write 108, write 110 and write 112. The data waveform is shown below the command waveform. In each of the valid data periods labeled 1-8, eight bits of data are transmitted. A data mask waveform is shown below the data waveform. The data mask waveform indicates the values being transmitted on the data mask lines. For write 108, the data mask line is high during the entire write. In this illustration, a low data mask bit, or a 0 logic level on a data mask line, indicates that the corresponding byte is to be written. So, for write 108, none of the bytes 108 are to be written.
Write 110 differs from write 108. Write 110 is a byte-write in which only particular bytes of the eight bytes are to be written. Referring to the data mask waveform for write 110, it can be seen that the data mask has a value of 10110111. Therefore, data mask pins and lines are required to be available for each write operation, even if byte-write operations make up a small percentage of write operations, as is often the case in many modern applications.
One approach to allowing byte-writes without the use of a dedicated mask pin is a reusable data mask. In DRAMs that support this capability, a memory controller can program the data mask into a register inside the DRAM and reuse it later. However, for many applications, including many graphics application, the number of reusable mask is small, so the performance improvement may not be very great.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 102 is first introduced and discussed with respect to FIG. 1).